02 · Capital Systems Integrator · Capital Logic Designer
Design rule checking
Can it find every rule violation in a wiring design, and nothing else?
Run five design rule checks over a wire list: unknown connectors, pins out of range, self-loops, shared cavities and gauges outside a terminal’s range. Scored on precision and recall, so a checker that flags everything scores as badly as one that flags nothing.
Capital reference. Design Rule Checks (systems-integrator/design-rule-checks). This domain stands for the capability that article describes; the task gives the model the rules in full rather than testing whether it remembers Capital’s.
Not tested here. Capital’s full rule catalogue, rule configuration, and checks over graphics or library data.
Scale ladder. S: 14 wires · M: 60 wires · L: 180 wires.
Results
| Model | Verdict | S passed | M passed | L passed | Mean score |
|---|---|---|---|---|---|
| Claude Opus 5.5 | Ready | 3 / 3 | 3 / 3 | 3 / 3 | 100 |
| Claude Fable 5.1 | Ready | 3 / 3 | 3 / 3 | 3 / 3 | 100 |
| Claude Sonnet 5.5 | Ready | 3 / 3 | 3 / 3 | 3 / 3 | 100 |
Every trial
| Model | Size | Seed | Score | Checks | Time |
|---|---|---|---|---|---|
| Claude Fable 5.1 | L#0 | 1796696020 | 100 | violations: 28 of 28 found, 0 false alarms · count: 28 reported, 28 present | 66 s |
| Claude Fable 5.1 | L#1 | 1813473639 | 100 | violations: 24 of 24 found, 0 false alarms · count: 24 reported, 24 present | 63 s |
| Claude Fable 5.1 | L#2 | 1830251258 | 100 | violations: 25 of 25 found, 0 false alarms · count: 25 reported, 25 present | 65 s |
| Claude Fable 5.1 | M#0 | 3383663519 | 100 | violations: 12 of 12 found, 0 false alarms · count: 12 reported, 12 present | 22 s |
| Claude Fable 5.1 | M#1 | 3366885900 | 100 | violations: 13 of 13 found, 0 false alarms · count: 13 reported, 13 present | 21 s |
| Claude Fable 5.1 | M#2 | 3417218757 | 100 | violations: 10 of 10 found, 0 false alarms · count: 10 reported, 10 present | 21 s |
| Claude Fable 5.1 | S#0 | 3390120513 | 100 | violations: 4 of 4 found, 0 false alarms · count: 4 reported, 4 present | 12 s |
| Claude Fable 5.1 | S#1 | 3373342894 | 100 | violations: 5 of 5 found, 0 false alarms · count: 5 reported, 5 present | 11 s |
| Claude Fable 5.1 | S#2 | 3356565275 | 100 | violations: 4 of 4 found, 0 false alarms · count: 4 reported, 4 present | 11 s |
| Claude Opus 5.5 | L#0 | 1796696020 | 100 | violations: 28 of 28 found, 0 false alarms · count: 28 reported, 28 present | 51 s |
| Claude Opus 5.5 | L#1 | 1813473639 | 100 | violations: 24 of 24 found, 0 false alarms · count: 24 reported, 24 present | 49 s |
| Claude Opus 5.5 | L#2 | 1830251258 | 100 | violations: 25 of 25 found, 0 false alarms · count: 25 reported, 25 present | 56 s |
| Claude Opus 5.5 | M#0 | 3383663519 | 100 | violations: 12 of 12 found, 0 false alarms · count: 12 reported, 12 present | 23 s |
| Claude Opus 5.5 | M#1 | 3366885900 | 100 | violations: 13 of 13 found, 0 false alarms · count: 13 reported, 13 present | 21 s |
| Claude Opus 5.5 | M#2 | 3417218757 | 100 | violations: 10 of 10 found, 0 false alarms · count: 10 reported, 10 present | 22 s |
| Claude Opus 5.5 | S#0 | 3390120513 | 100 | violations: 4 of 4 found, 0 false alarms · count: 4 reported, 4 present | 13 s |
| Claude Opus 5.5 | S#1 | 3373342894 | 100 | violations: 5 of 5 found, 0 false alarms · count: 5 reported, 5 present | 11 s |
| Claude Opus 5.5 | S#2 | 3356565275 | 100 | violations: 4 of 4 found, 0 false alarms · count: 4 reported, 4 present | 12 s |
| Claude Sonnet 5.5 | L#0 | 1796696020 | 100 | violations: 28 of 28 found, 0 false alarms · count: 28 reported, 28 present | 45 s |
| Claude Sonnet 5.5 | L#1 | 1813473639 | 100 | violations: 24 of 24 found, 0 false alarms · count: 24 reported, 24 present | 46 s |
| Claude Sonnet 5.5 | L#2 | 1830251258 | 100 | violations: 25 of 25 found, 0 false alarms · count: 25 reported, 25 present | 41 s |
| Claude Sonnet 5.5 | M#0 | 3383663519 | 100 | violations: 12 of 12 found, 0 false alarms · count: 12 reported, 12 present | 18 s |
| Claude Sonnet 5.5 | M#1 | 3366885900 | 100 | violations: 13 of 13 found, 0 false alarms · count: 13 reported, 13 present | 16 s |
| Claude Sonnet 5.5 | M#2 | 3417218757 | 100 | violations: 10 of 10 found, 0 false alarms · count: 10 reported, 10 present | 19 s |
| Claude Sonnet 5.5 | S#0 | 3390120513 | 100 | violations: 4 of 4 found, 0 false alarms · count: 4 reported, 4 present | 9 s |
| Claude Sonnet 5.5 | S#1 | 3373342894 | 100 | violations: 5 of 5 found, 0 false alarms · count: 5 reported, 5 present | 8 s |
| Claude Sonnet 5.5 | S#2 | 3356565275 | 100 | violations: 4 of 4 found, 0 false alarms · count: 4 reported, 4 present | 7 s |
What the model is asked
The small instance at seed 3390120513, exactly as sent. Regenerate any instance with npm run sample -- drc M 2.
Show the prompt (2,477 characters)
TASK: Design rule check.
Check this wire list against exactly these five rules. Report every (rule, wire) pair that fails.
- UNKNOWN_CONNECTOR: an end names a connector that is not in the connector list. (Skip the other checks for that end.)
- PIN_RANGE: an end names a pin below 1 or above that connector’s pin count. (Skip GAUGE_RANGE and CAVITY_SHARED for that end.)
- SELF_LOOP: both ends of one wire are the same connector and pin.
- CAVITY_SHARED: two or more DIFFERENT wires land on the same connector pin. Report every wire involved. A self-loop wire alone does not count as shared.
- GAUGE_RANGE: the wire gauge is outside the connector’s gaugeRange [min, max] (inclusive) at either end.
A wire that breaks the same rule at both ends is reported once for that rule.
Connectors:
[
{"id":"J1","pins":16,"gaugeRange":[18,24]},
{"id":"J2","pins":24,"gaugeRange":[20,26]},
{"id":"J3","pins":22,"gaugeRange":[20,26]},
{"id":"J4","pins":11,"gaugeRange":[14,20]}
]
Wires:
[
{"id":"W1","from":{"connector":"J2","pin":5},"to":{"connector":"J3","pin":16},"gauge":24},
{"id":"W2","from":{"connector":"J3","pin":5},"to":{"connector":"J3","pin":5},"gauge":20},
{"id":"W3","from":{"connector":"J1","pin":3},"to":{"connector":"J2","pin":13},"gauge":16},
{"id":"W4","from":{"connector":"J2","pin":12},"to":{"connector":"J4","pin":10},"gauge":20},
{"id":"W5","from":{"connector":"J3","pin":12},"to":{"connector":"J1","pin":16},"gauge":22},
{"id":"W6","from":{"connector":"J4","pin":8},"to":{"connector":"J3","pin":4},"gauge":12},
{"id":"W7","from":{"connector":"J4","pin":11},"to":{"connector":"J2","pin":8},"gauge":20},
{"id":"W8","from":{"connector":"J3","pin":18},"to":{"connector":"J4","pin":7},"gauge":20},
{"id":"W9","from":{"connector":"J3","pin":20},"to":{"connector":"J2","pin":16},"gauge":20},
{"id":"W10","from":{"connector":"J3","pin":15},"to":{"connector":"J1","pin":6},"gauge":24},
{"id":"W11","from":{"connector":"J3","pin":1},"to":{"connector":"J2","pin":22},"gauge":20},
{"id":"W12","from":{"connector":"J2","pin":2},"to":{"connector":"J1","pin":9},"gauge":20},
{"id":"W13","from":{"connector":"J1","pin":13},"to":{"connector":"J2","pin":1},"gauge":20},
{"id":"W14","from":{"connector":"J1","pin":8},"to":{"connector":"J3","pin":22},"gauge":16}
]
Output format (JSON, exactly these keys):
```json
{
"violations": [
{
"rule": "PIN_RANGE",
"wire": "W12"
}
]
}
```
An empty list is a valid answer if the design is clean.